Role description

DFT Engineer Intern

Ambarella

TypeInternship

SeniorityIntern

LocationUS Headquarters

Posted8/27/2026

Engineering

AI Vision Processors For Edge Applications

Our solutions make cameras smarter by extracting valuable data from high-resolution video streams.

Job Description

Position Responsibilities:

Logic Design to support DFT features
Automate DFT Flows (Scan, Compression & MBIST) used for complex multi-million gate SoC
Verification of DFT Logic and analysis of fault coverage
Timing analysis for DFT Modes

Minimum Requirements:

MSEE in Electrical / Computer Engineering
Knowledge of DFT fundamentals
Knowledge of Logic design & Static timing analysis
Knowledge of Verilog and any scripting language
Knowledge of AI assisted programming

Relevant archetypes

Apply on Workday

Company info

Ambarella

Ambarella is an AI vision silicon company.

With an installed base of more than 50 million AI SoC units, Ambarella’s products are utilized in a wide variety of physical edge AI applications, spanning edge endpoint and edge infrastructure use cases including physical security, vehicle safety, telematics, autonomy, portable video, aerial drones, and other emerging robotic applications. Building on this footprint, Ambarella offers a full-stack edge AI platform, from highly optimized silicon and programmable software to AI agentic frameworks that coordinate perception, decision-making and control across devices. Ambarella’s low-power systems-on-chip (SoCs) integrate proprietary and highly efficient perception and deep learning neural network AI accelerators, enabling electronic systems to become more productive with partial or complete levels of machine autonomy.

Founded2004

HQSanta Clara, United States

Size501–1,000 employees