Senior FPGA Developer

AscendArc is a venture-backed startup transforming the future of satellite communications by fundamentally changing the economics of GEO satellites. We’re developing a new approach to satellite design and production to deliver dramatically better bandwidth economics and expand access to reliable, affordable connectivity around the world. 

Position Summary

We are seeking an experienced Senior FPGA Developer to play a critical role in developing and advancing the communications technology behind our next-generation spacecraft. This is an opportunity to take ownership of FPGA development, working across digital signal processing, software-defined radio (SDR), and spacecraft integration.

You'll work with existing modulation, demodulation, and packet-switching IP cores, bringing these systems together while developing custom DSP functionality and the interfaces that allow the spacecraft to command, control, and communicate with the radio. Beyond hands-on RTL development, you'll have the opportunity to influence technical direction, solve complex engineering challenges, and help shape the future of our communications architecture.

This is a highly collaborative, hands-on role for an engineer who enjoys technical ownership, solving challenging problems, and seeing their work move from design all the way to orbit.

Responsibilities

Architect, write, and verify synthesizable RTL (SystemVerilog or VHDL) targeting modern FPGAs.

Integrate and configure existing modulation and demodulation, and packet-switching/routing IP cores — parameterizing ports, configuring routing tables, wiring up flow control and error/status interfaces, and validating end-to-end behavior in the surrounding design. Implement DSP blocks in fabric: FIR/CIC/polyphase filters, NCOs and mixers, decimation/interpolation chains, channelizers, and demodulation/synchronization logic.

Develop simulation testbenches (UVM, cocotb, or similar), drive functional and code coverage, and own bring-up on hardware. Take designs through synthesis, place-and-route, and timing closure; analyze utilization, congestion, and Fmax issues and resolve them at the RTL level. Integrate with ADC/DAC front-ends and other mixed-signal interfaces, including clocking, calibration, and lane alignment. Collaborate with systems, firmware, and hardware engineers on interface definitions and HW/SW partitioning. Produce design documentation, interface control documents, and verification reports.

Required Qualifications

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or equivalent experience.
• 8+ years of professional FPGA development in SystemVerilog and/or VHDL.
• Demonstrated experience integrating third-party or vendor IP cores into larger FPGA designs — reading datasheets and user guides, configuring parameters, adapting interfaces, and verifying integrated behavior.
• Working understanding of packet-based routing and switching concepts (arbitration, buffering, backpressure, link-layer framing) sufficient to integrate and debug routing IP, even if not designing the switch fabric itself.
• Strong DSP fundamentals and hands-on experience implementing signal processing in fixed-point HDL: filter design, sample-rate conversion, numerically controlled oscillators, and digital down/up-conversion.
• Practical experience with high-speed serial transceivers (e.g., GTH/GTY, equivalent Intel transceivers) including 8b/10b or 64b/66b encoding, comma alignment, and lane bonding.
• Proficiency with the full Vivado toolchain: synthesis, implementation, timing analysis (STA), and constraint authoring (XDC/SDC).
• Strong verification skills, including self-checking testbenches, constrained-random stimulus, and coverage-driven methodology. Comfort with Git-based workflows and code review.

Preferred Qualifications

• RF and analog front-end experience — working knowledge of RF chains, frequency planning, mixing, image rejection, and the interaction between analog impairments and digital correction.
• Experience with high-speed converter interfaces such as JESD204B/C, including link bring-up and deterministic latency.
• Experience with space, defense, or other high-reliability environments, including radiation-tolerant design practices, TMR, scrubbing, and SEU mitigation.
• Familiarity with AXI/AXI-Stream interconnect and DMA architectures.
• Background in clock-domain crossing methodology and formal verification of CDC. Experience supporting hardware bring-up with lab instrumentation (logic analyzers, spectrum analyzers, signal generators).

Location

• Open to fully remote within the United States or hybrid in Portland, OR

Compensation

The base pay range for this role is $180,000 – $230,000 per year.