Senior FPGA Development Engineer

Radar Reinvented.

Echodyne offers the world’s first compact solid-state true beam-steering radar for a wide range of industries and applications. Our high-performance radars work in all weather and are designed for autonomous vehicles, uncrewed aircraft & drones, and security of borders, critical infrastructure, and smart cities. The company combines the patented technology of metamaterials with powerful software to create a radar sensor with unprecedented performance at commercial price points. Echodyne offers its radars to companies working in Automotive, Transportation, Critical Infrastructure Protection, Border Security, Smart Cities, Uncrewed Aircraft Systems (UAS), and Airspace Management including Urban Air Mobility (UTM).

Echodyne is seeking a Senior FPGA Development Engineer – Design and produce radar equipment subsystems composed of Echodyne’s industry-leading radars.   

ROLE OVERVIEW

In this role, you will engage with an experienced cross-disciplinary team to create radar systems solutions thought high-performance, secure software solutions. 

You will work closely with colleagues to design and build FPGA solutions, mentor junior engineers, and play a key role in shaping the HDL development practices of the team. This role demands technical ownership, systems knowledge, and a strong quality embedded development mindset. You must be responsive, flexible, and able to succeed within a collaborative and fast-paced environment. 

RESPONSIBILITIES

• Architect, design, implement, integrate, and test FPGA-based solutions. 
• Write efficient, robust, timing optimized, and maintainable VHDL/Verilog code.  
• Take responsibility and assume ownership for tasks; seeking guidance when needed.  
• Develop and execute a plan of action based on design requirements and constraints.  
• Hold and participate in design reviews and peer reviews.  
• Work with and support team members, both technical and non-technical. Representing yourself to others with a high level of integrity and professionalism.
• Drive improvements to coding practices and tools across engineering.
• Design and develop reusable cross platform architectures and frameworks.
• Help drive and support testing efforts across teams and projects.
• Work alongside radar, signal processing, and software engineers to implement platform functionality to meet specific system control and signal processing needs.
• Mentor and provide technical direction to junior developers. 

REQUIRED SKILLS / EXPERIENCE

• Proficient at communicating your ideas, plans and designs to teammates.
• Skilled at delineating scope, preparing work plans, resolving design conflicts, and overseeing design implementation steps.
• Solid understanding of FPGA architectures (DSP, SoC), their hardware/software interfaces, and memory interfaces (DDR, SRAM, Flash).
• Experienced user of FPGA design tools and methodologies, including: simulators and static code analyzers. Specifically: Vivado, Quartus, QuestaSim, Blue Pearl, design documentation software, configuration management software (JIRA), and version control software (Git).
• Embedded systems debugging, troubleshooting, and code-testing knowledge using JTAG debuggers, oscilloscopes, logic analyzers, multi-meters, spectrum analyzers.
• Knowledge of Python, tcl, or other scripting languages for development and testing automation.
• Knowledge of software development life cycle, and good coding practices  
• Interfacing embedded systems to host computers and peripherals, using common communications protocols (UART, SPI, QSPI, I2C, TCP/UDP IP)
• Experience with common interfaces such as: AXI, AXI-Stream. 

DESIRED SKILLS / EXPERIENCE 
(Looking for one or more as a complement to the core skills) 

• Experience with one or more high speed interfaces (CML, LVDS, JESD, SERDES, Ethernet/UDP, Aurora, PCI-E)
• Working DSP knowledge including: developing HDL for Radar, Electronic Warfare, Cellular, or other Wireless Technology.  
• Experience in fixed-point math, implementation, tradeoffs, and modeling (Matlab or scipy is a plus).
• Capable of leading a project team of three or more engineers within the discipline or across disciplines.
• Familiar with continuous integration, HIL testing, and Agentic AI workflows. 

QUALIFICATIONS

• Bachelor of Science degree in electrical engineering, computer engineering, computer science or equivalent military / industry experience 
• 5+ years of designing, implementing, building, integrate and testing Verilog/System Verilog and VHDL software solutions. 
• Working knowledge of hardware/PCB design and embedded software and verification. 

Echodyne’s technology is export controlled by the U.S. Government and we must evaluate an applicant’s eligibility to handle export-controlled information or obtain required Government authorizations.  Therefore, we will ask you as part of the application process to identify whether you are a U.S. Citizen or green card holder, or have asylum/refugee status in the U.S. 

WHAT WE OFFER

This is an exempt role.
The salary range for this position is $137,196 - $205,382 per year. 

If your skills generally align but not perfectly, please apply anyway. There may be another role that’s a great fit for you!

We offer competitive compensation and benefits to our full-time, US-based employees, including:

• RSU (Restricted Stock Units)
• Generous Benefits:
• Fully-paid medical, dental, and vision insurance premiums for you 
• Choice of PPO or HDHP/HSA
• Virtual Care – 98Point6
• Employee Assistance Program
• Mental Health coverage through Springhealth & Talkspace (Premera)
• Travel Assistance Insurance
• Company Paid Life Insurance
• Company Paid Short & Long Term Disability
• Flexible PTO (exempt) / 15 days per year (non-exempt)
• 401(k) match
• Pet Insurance
• Prepaid Legal Program
• Commuter Benefits
• Paid Company Holidays

All qualified applicants receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, age, status as a protected veteran or any other characteristic protected by law.