Job Details:
Job Description:
- Strong knowledge and experience in Spyglass DFT, Scan Architecture (SSN Topology), ATPG and various fault models.
- Hands on skills to implement JTAG, Memory BIST and Memory Repair (BIRA/BISR) circuitry using industry standard tools.
- Hands on experience in DFT verification using Gate Level Simulations with timing annotations.
- Hands on experience in solving DFT problems, simulation failures, ATPG coverage improvements and DRC debug.
- Good understanding of timing constraints and DFT mode timing analysis.
- Proficiency in RTL coding, shell scripting.
- Experience working with post-Silicon/manufacturing teams on ATE, including debugging and resolving issues.
Qualifications:
B.E/B.Tech/M.E/M.Tech in Electrical/Electronics/Communication Engineering with 2+ years of DFT experience.
Job Type:
Intel Contract Employee
Shift:
Shift 1 (India)
Primary Location:
India, Bangalore
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
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